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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\yami\Documents\RVX32\src\RxV32.v<br>
C:\Users\yami\Documents\RVX32\src\gowin_sp\gowin_sp.v<br>
C:\Users\yami\Documents\RVX32\src\main.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NZ-LV1QN48C6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NZ-1</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Nov 29 14:47:19 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>RxV32_main</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.222s, Peak memory usage = 121.816MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 121.816MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 121.816MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 121.816MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 121.816MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 121.816MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 5s, Peak memory usage = 121.816MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>11</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>391</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>104</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>175</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>13</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>60</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>33</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>840</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>75</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>273</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>492</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>193</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>193</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>5</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSP</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>3</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>1038(845 LUTs, 193 ALUs) / 1152</td>
<td>90%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>391 / 957</td>
<td>41%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 957</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>391 / 957</td>
<td>41%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>4 / 4</td>
<td>100%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>n177_6</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>n177_s2/O </td>
</tr>
<tr>
<td>rv_data_w_Z</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>rv32/data_w_s0/Q </td>
</tr>
<tr>
<td>n79_3</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>n79_s0/F </td>
</tr>
<tr>
<td>cpu_clk_exec</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>rv32/cpu_clk_exec_s0/F </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.0(MHz)</td>
<td>86.8(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>n79_3</td>
<td>50.0(MHz)</td>
<td>109.9(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>cpu_clk_exec</td>
<td>50.0(MHz)</td>
<td>281.8(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>19.963</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_321_DIAREG_G_20_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/PC_8_s0/CLK</td>
</tr>
<tr>
<td>0.821</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>rv32/PC_8_s0/Q</td>
</tr>
<tr>
<td>1.301</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1052_s3/I1</td>
</tr>
<tr>
<td>2.400</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n1052_s3/F</td>
</tr>
<tr>
<td>2.880</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1037_s5/I1</td>
</tr>
<tr>
<td>3.979</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>12</td>
<td>rv32/n1037_s5/F</td>
</tr>
<tr>
<td>4.459</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1042_s2/I1</td>
</tr>
<tr>
<td>5.558</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rv32/n1042_s2/F</td>
</tr>
<tr>
<td>6.038</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2955_s1/I0</td>
</tr>
<tr>
<td>7.070</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2955_s1/F</td>
</tr>
<tr>
<td>7.550</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2955_s0/I0</td>
</tr>
<tr>
<td>8.582</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2955_s0/F</td>
</tr>
<tr>
<td>9.062</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_20_s/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>20.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_20_s/CLK</td>
</tr>
<tr>
<td>19.963</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_20_s</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.361, 61.625%; route: 2.880, 33.106%; tC2Q: 0.458, 5.269%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>19.963</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_321_DIAREG_G_18_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/PC_8_s0/CLK</td>
</tr>
<tr>
<td>0.821</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>rv32/PC_8_s0/Q</td>
</tr>
<tr>
<td>1.301</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1052_s3/I1</td>
</tr>
<tr>
<td>2.400</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n1052_s3/F</td>
</tr>
<tr>
<td>2.880</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1037_s5/I1</td>
</tr>
<tr>
<td>3.979</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>12</td>
<td>rv32/n1037_s5/F</td>
</tr>
<tr>
<td>4.459</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1044_s2/I1</td>
</tr>
<tr>
<td>5.558</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rv32/n1044_s2/F</td>
</tr>
<tr>
<td>6.038</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2957_s1/I0</td>
</tr>
<tr>
<td>7.070</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2957_s1/F</td>
</tr>
<tr>
<td>7.550</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2957_s0/I0</td>
</tr>
<tr>
<td>8.582</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2957_s0/F</td>
</tr>
<tr>
<td>9.062</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_18_s/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>20.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_18_s/CLK</td>
</tr>
<tr>
<td>19.963</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_18_s</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.361, 61.625%; route: 2.880, 33.106%; tC2Q: 0.458, 5.269%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>19.963</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_321_DIAREG_G_16_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/PC_8_s0/CLK</td>
</tr>
<tr>
<td>0.821</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>rv32/PC_8_s0/Q</td>
</tr>
<tr>
<td>1.301</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1052_s3/I1</td>
</tr>
<tr>
<td>2.400</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n1052_s3/F</td>
</tr>
<tr>
<td>2.880</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1037_s5/I1</td>
</tr>
<tr>
<td>3.979</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>12</td>
<td>rv32/n1037_s5/F</td>
</tr>
<tr>
<td>4.459</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n1046_s2/I1</td>
</tr>
<tr>
<td>5.558</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rv32/n1046_s2/F</td>
</tr>
<tr>
<td>6.038</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2959_s1/I0</td>
</tr>
<tr>
<td>7.070</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2959_s1/F</td>
</tr>
<tr>
<td>7.550</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2959_s0/I0</td>
</tr>
<tr>
<td>8.582</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2959_s0/F</td>
</tr>
<tr>
<td>9.062</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_16_s/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>20.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_16_s/CLK</td>
</tr>
<tr>
<td>19.963</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_16_s</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.361, 61.625%; route: 2.880, 33.106%; tC2Q: 0.458, 5.269%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>11.014</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.919</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>19.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_321_DIAREG_G_31_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>cpu_clk_exec[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/rx32x/rd_write_2_s0/CLK</td>
</tr>
<tr>
<td>0.821</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>rv32/rx32x/rd_write_2_s0/Q</td>
</tr>
<tr>
<td>1.301</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s3/I1</td>
</tr>
<tr>
<td>2.400</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s3/F</td>
</tr>
<tr>
<td>2.880</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s1/I1</td>
</tr>
<tr>
<td>3.979</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2910_s1/F</td>
</tr>
<tr>
<td>4.459</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s2/I1</td>
</tr>
<tr>
<td>5.558</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>rv32/n2910_s2/F</td>
</tr>
<tr>
<td>6.038</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2944_s1/I1</td>
</tr>
<tr>
<td>7.137</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2944_s1/F</td>
</tr>
<tr>
<td>7.617</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2944_s0/I2</td>
</tr>
<tr>
<td>8.439</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2944_s0/F</td>
</tr>
<tr>
<td>8.919</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_31_s/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>20.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_31_s/CLK</td>
</tr>
<tr>
<td>20.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>rv32/REG_321_DIAREG_G_31_s</td>
</tr>
<tr>
<td>19.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_31_s</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.218, 60.984%; route: 2.880, 33.659%; tC2Q: 0.458, 5.357%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>11.014</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.919</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>19.933</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_321_DIAREG_G_30_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>cpu_clk_exec[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/rx32x/rd_write_2_s0/CLK</td>
</tr>
<tr>
<td>0.821</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>rv32/rx32x/rd_write_2_s0/Q</td>
</tr>
<tr>
<td>1.301</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s3/I1</td>
</tr>
<tr>
<td>2.400</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s3/F</td>
</tr>
<tr>
<td>2.880</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s1/I1</td>
</tr>
<tr>
<td>3.979</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2910_s1/F</td>
</tr>
<tr>
<td>4.459</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2910_s2/I1</td>
</tr>
<tr>
<td>5.558</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>rv32/n2910_s2/F</td>
</tr>
<tr>
<td>6.038</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2945_s1/I1</td>
</tr>
<tr>
<td>7.137</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2945_s1/F</td>
</tr>
<tr>
<td>7.617</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/n2945_s0/I2</td>
</tr>
<tr>
<td>8.439</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rv32/n2945_s0/F</td>
</tr>
<tr>
<td>8.919</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_30_s/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>20.363</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_30_s/CLK</td>
</tr>
<tr>
<td>20.333</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>rv32/REG_321_DIAREG_G_30_s</td>
</tr>
<tr>
<td>19.933</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rv32/REG_321_DIAREG_G_30_s</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.218, 60.984%; route: 2.880, 33.659%; tC2Q: 0.458, 5.357%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.363, 100.000%</td></tr>
</table>
<br/>
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